1. Field of the Invention
The present invention relates to video digital to analog converters (video DACs) and more particularly to current steering video DAC in which the current is periodically turned off to reduce power dissipation.
2. State of the Art
In computer display systems, display information is represented in computer memory by what may be imagined as a three dimensional array of binary digits. The first two dimensions correspond to the dimensions of the computer display in terms of pixel elements. For example, if the computer display has 640.times.480 picture elements, these picture elements are represented in computer memory by what may be conceived of as a 640.times.480 array of binary digits, or bits. For grayscale and color displays, the third dimension of the array of binary digits corresponds to the intensity with which each pixel is to be displayed. For example, if each picture element is to be displayed at one of256 different possible intensities, then 8 bits are required for each pixel to represent the intensity of that pixel. To display the image on the computer display, a series of 8-bit words each representing the intensity of a single pixel is read out of the computer memory and applied to a digital-to-analog converter to produce a signal of corresponding intensity.
In the case of a color display, each 8-bit word is first applied to a color look-up table stored in random access memory. Contained in the color look-up memory are expanded digital words representing a sub-set (palette) of active display colors of a set of possible colors. The expanded digital words are logically divided into three portions, each corresponding to a primary display color such as red, green or blue. Each of these portions of the overall digital word is input to a separate digital-to-analog converter corresponding to a particular primary color to produce analog red, green and blue display signals.
To perform digital-to-analog conversion, an incremental voltage or current is added to a cumulative voltage or current for each possible digital value up to and including the digital value being converted. Of overriding importance is that the incremental voltage or incremental current be substantially constant. To generate the aforementioned incremental voltage or current, digital-to-analog converters require that a reference voltage or reference current be input to the digital-to-analog converter. From a reference voltage or reference current, a reference generator of the digital-to-analog converter then generates the incremental voltage or current.
Recently, single-chip graphics subsystems have been developed that provide a higher level of integration than previous graphics subsystems in order to reduce system cost and to save valuable board space in both laptop and notebook computer applications. A single-chip graphics subsystem typically consists of a graphics controller with hardware accelerator, a RAMDAC (i.e., a combination random access memory and digital to analog converter) and frequency synthesizers. To provide high video resolution, the RAMDAC must operate at high speeds. The accompanying high power dissipation of a high speed RAMDAC has been a significant problem in developing highly-integrated single-chip graphics subsystems.
Furthermore, the PC industry has recently adopted a new "Green PC" standard for desktop computers intended to lessen the environmental impact of personal computers. An object of the standard is to bring all personal computers into compliance with low power design requirements.
Attempts have been made to reduce the power dissipation of video DACs based on the recognition that, during the blanking period of an active video display, no current outputs from the three main DAC current sources are required. Therefore, all three DAC current sources may be turned off during the blanking period in order to reduce power consumption without affecting the normal operation of the screen.
A conventional current steering DAC with power-down capability is shown in FIG. 1. Referring to FIG. 1, a triple-DAC (digital to analog converter) portion 20 of the circuit of FIG. 1 includes a transistor pair M11 and M12 for generating a red signal at node IOR, a transistor pair M21 and M22 for generating a green signal at node IOG signal and a transistor pair M31 and M32 for generating a blue signal at node IOB. Current to the respective transistor pairs is supplied by respective ones of transistors M1, M2 and M3. In the illustrated embodiment, all of the transistors are P-channel MOSFETs. The sources of transistors M1, M2 and M3 are connected to a supply voltage VDD, and the gates of transistors M2, M3, M4 are connected through a control switch S1 to a control signal 13 generated by a reference generator portion 30 of the circuit. In response to the control signal 13, each of the transistors M1, M2 and M3 produces a current I that is input to the source of a respective one of the transistor pairs M11/M12, M21/M22, and M31/M32. The drain of one transistor (M11, M21 and M31) of each pair of transistors is connected to a load resistor (R.sub.L1, R.sub.L2, and R.sub.L3, respectively) connected between an output signal terminal for one of the primary colors and ground, and the gates of the same transistors are connected to the complements of data bits representing the desired intensities of the corresponding primary colors. The drain of the other transistor (M12, M22, and M32) of each of pair of transistors is connected to ground, and the gates of the same transistors are connected to the true form of the data bits. Therefore, when the red data bit RDATA is a 0, the current I is shunted to ground through transistor M12, and when the red data bit RDATA is a 1, the current I is output to the red output terminal through the transistor M11.
For simplicity, only one cell of the digital-to-analog converter is shown for each of the primary colors. In actual practice, the cells are repeated a number of times equal to the number of possible input values. For example, if 256 digital input values are possible, the cells may be imagined as being stacked 256 deep in a direction into the page. Half of the cells would be controlled in accordance with the most significant data bit, half of the remaining cells would be controlled in accordance with the next most significant data bit, and so forth. For each of the primary colors, the output currents for each of the cells are combined and used to produce a corresponding output voltage at the respective output terminal IOR, IOG, or IOB.
Hence, during active operation, the gates of each pass transistor pair (i.e., M11 and M12, M21 and M22, M31 and M32) are driven by complementary signal pairs (i.e., RDATA and RDATA, GDATA and GDATA, BDATA and BDATA). The currents from the three current-sources (i.e., M1, M2 and M3) are steered either into the external resistive loads (i.e., R.sub.L1, R.sub.L2 and R.sub.L3) by turning the pass transistors M11, M21 and M31 on and M12, M22 and M32 off, or into ground (i.e., VSS) by turning the pass transistors M12, M22 and M32 on and M11, M21 and M32 off.
During video blanking, the DAC is placed in a power-conserving sleep mode. Conventionally, to place the DAC in sleep mode (or into power-down operation), the gates of the P-channel current sources (i.e., M1, M2 and M3) are shorted to the VDD terminal by opening the switch S1 and closing the switch S2 in accordance with a control signal SLEEP. The control signal SLEEP is generated from the composite blanking signal in the graphics subsystem. The SLEEP signal is active high during the blanking period and becomes low when the blanking signal is inactive. However, the three current sources (i.e., M1, M2 and M3 of FIG. 1) will wake up slowly after the blanking signal goes inactive due to a large compensation capacitor C.sub.C in the reference generator portion 30 of the DAC. The compensation capacitor C.sub.C (typically about 0.1 .mu.F) is connected to the gates of the current sources through the control line 13, causing the gates of the current sources to exhibit a large time constant. This large time constant causes a large time delay in the resumption of the active video signal, distorting the video picture. Therefore, the conventional circuit is not suitable for dynamic power saving applications.
What is needed, then, is a way to reduce the high power dissipation of a high-speed video DAC without compromising its performance.